1. Field of the Invention
The invention relates to memory controllers utilized in computer systems, and more particularly, to computer systems which allow multiple sources to access a given block or portion of memory.
2. Description of the Related Art
Personal computer systems are getting more and more powerful at a very rapid rate. One reason for this increase in power is the development and availability of more powerful microprocessors, which form the basis of the personal computers. New microprocessor designs are being developed and the clock rates of the existing microprocessors are being increased so that more and more performance is available.
With the development of 32 bit microprocessors, the main memory was separated from the physical slots provided for interchangeable boards which were generally only 8 or 16 bits wide. By separating the main memory array it became possible to make the memory array 32 bits wide and to run at significantly higher speeds then what otherwise would have been possible over the bus connecting the slots. However, to utilize this memory array a memory controller was required which could handle cycles coming from the processor and cycles which were generated over the interchangeable circuit board bus. To this end various types of memory controllers were designed for various systems. For instance, for systems according to the industry standard architecture (ISA) based on the International Business Machines Corporation (IBM) PC/AT, synchronous memory controllers were utilized based on the clock provided to the microprocessor. For systems according to the Micro Channel Architecture (MCA) developed by IBM asynchronous memory controllers were developed because this bus definition was an asynchronous design, in deference to the synchronous design of the ISA.
One problem with synchronous controllers is that with each change in microprocessor, either architecture or speed, the memory controller must be redesigned. This leads to great complications in each design. While an asynchronous design can be developed, as in the MCA, these designs are not necessarily optimized for use with a different processor and therefore there would be performance degradation as compared to the ultimate limits possible based on given memory devices. Therefore even an asynchronous design has to be revised with each new microprocessor. Thus system designers were left with the choice of having to redesign the memory controller each time a new processor was utilized, incorporating both processor related functions and bus related functions, or to use an asynchronous design with inherent trade offs in system performance.